Digital Down Converter COFDM ความถี่การถ่ายโอน 2.4G ถึง 600Mhz BDC ต่ำ

ตัวแปลงดิจิตอลลง

Digital Down Converter COFDM Transfer frequency 2.4G to 600Mhz low

จุดขาย

1. Input frequencies from 24000 to 600MHz (Lower 1800Mhz)
2. High bandwidth
3. Low phase noise
4. High-frequency stability

สเปค

RF Frequency Range： 2400 Mhz
IF Frequency Range： 600 Mhz
Return Loss：-12 เดซิเบล
Frequency Accuracy: ±10 ppm
Image Rejection: 60 dBc
Flatness: ±0.5 เดซิเบล (8MHz bandwidth)
กำไรการแปลง: 25 เดซิเบล
Phase Noise (เดซิเบล/เฮิร์ตซ์)
dBc/Hz@1KHz ≤-80
dBc/Hz@10KHz ≤-90
dBc/Hz@100KHz ≤-100
การจ่ายแรงดัน: 10~15V
Power Current: 100 mA
Operating Temperature Range: +25 ℃

 

Port

อาร์เอฟ อิน: SMA-50K
IF OUT: SMA-50K
Power +12V: Stick
GND: Soldering lug

บันทึก

1. The converter does not need to add a low noise amplifier at the back end.
2. Actual Test: closed-loop test under the frequency of 2.4GHz/bandwidth 4MHz, the receiving sensitivity can reach -105dBm.
3. Input frequency supports 1~3GHz. (We can support customize).
4. Output frequency supports 300~700MHz. (We can support customize).

คำถามที่พบบ่อย

คำถาม: My input frequency range would need to be 2.0Ghz to 2.7Ghz, downconverting to 200Mhz to 900Mhz. The conversion gain would ideally be 30db not 25db. Would this be easy for you to do?

ตอบ: ใช่, we can customize for you.

What is DDC

In digital signal processing, a digital down-converter (ดีดีซี) converts a digitized, band limited signal to a lower frequency signal at a lower sampling rate in order to simplify the subsequent radio stages. The process preserves all the information in the original signal less that which is lost to rounding errors in the mathematical processes. The input and output signals can be real or complex samples. Often the DDC converts from the raw radio frequency or intermediate frequency down to a complex baseband signal.

Architecture

A DDC consists of three subcomponents: a direct digital synthesizer (DDS), a low-pass filter (LPF), and a downsampler (which may be integrated into the low-pass filter). The DDS generates a complex sinusoid at the intermediate frequency (ถ้า). Multiplication of the intermediate frequency with the input signal creates images centered at the sum and difference frequency (which follows from the frequency shifting properties of the Fourier transform). The lowpass filters pass the difference (i.e. baseband) frequency while rejecting the sum frequency image, resulting in a complex baseband representation of the original signal. Assuming judicious choice of IF and LPF bandwidth, the complex baseband signal is mathematically equivalent to the original signal. In its new form, it can readily be downsampled and is more convenient to many DSP algorithms. Any suitable low-pass filter can be used including FIR, IIR and CIC filters. The most common choice is a FIR filter for low amounts of decimation (less than ten) or a CIC filter followed by a FIR filter for larger downsampling ratios.

Variations on the DDC

Several variations on the DDC are useful, including many that input a feedback signal into the DDS. These include:

1. Decision directed carrier recovery phase locked loops in which the I and Q are compared to the nearest ideal constellation point of a PSK signal, and the resulting error signal is filtered and fed back into the DDS
2. A Costas loop in which the I and Q are multiplied and low pass filtered as part of a BPSK/QPSK carrier recovery loop

Implementation
DDCs are most commonly implemented in logic in field-programmable gate arrays or application-specific integrated circuits. While software implementations are also possible, operations in the DDS, multipliers and input stages of the lowpass filters all run at the sampling rate of the input data. This data is commonly taken directly from analog to digital converters (ADCs) sampling at tens or hundreds of MHz. CORDICs are an alternative to the use of multipliers in the implementation of digital down converters.

Wireless Video transmitter and receiver, COFDM-904T แนะนำ.